Daniel Keller

Daniel Keller is a PhD student in Electrical and Communications Engineering at ETH Zürich, specializing in digital IC design, ML accelerators, and ultra-low-power SoC development. He is an active contributor to the open-source PULP platform and has professional experience in both analog/mixed-signal and digital IC design, including full RTL-to-GDSII flow, SystemVerilog, and HLS.

Feel free to reach out for collaborations or opportunities via email or LinkedIn.